The present invention relates to an externally synchronized programmable device in which a desired circuit can be easily programmed and/or reprogrammed by a circuit designer, and an internal circuit of the device is made to operate in synchronism with the phase or frequency of an external signal.
Programmable logic devices which can be easily programmed or reprogrammed by a circuit designer to correspond to a desired circuit specification are well known. Such programmable logic devices, which are composed of matrices of AND and OR gates, can be programmed to realize a logic circuit having a two-stage AND-OR structure. Further, the circuit can be changed or reconstructed by reprogramming the device. Accordingly, the device has many general purpose usages.
The programmable logic device can not only realize a random logic circuit, but also it can realize a sequential circuit by feeding the output of an AND matrix or the output of an internal flip-flop circuit back to the input side of the AND matrix. Accordingly, the device is suitable for use in controllers such as sequential controllers or various kinds of instrumentation apparatuses.
In general, conventional programmable logic devices have a configuration as shown in FIG. 8. As shown in FIG. 8, an AND matrix 1 having input signal lines L.sub.1 -L.sub.m (represented by a group of vertical lines) and term lines l.sub.1 -l.sub.n (represented by a group of horizontal lines) arranged to intersect the input signal lines are provided. They permit a desired logic circuit to be constructed by programming lattice points formed at the intersections. The device further contains an OR matrix (functionally represented by multiple-input OR gates OR.sub.1 -OR.sub.i in the drawing) conjugated through the AND output (functionally represented by AND gates) produced on the AND term lines l.sub.1 -l.sub.n. Further, general input ports I.sub.1 -I.sub.j are provided for supplying logic signals from the outside to a part of the input signal lines L.sub.1 -L.sub.m, a clock input terminal CLK for receiving a clock signal supplied thereto, output ports for feeding the output signals of the OR matrix (multiple-input OR gates OR.sub.1 -OR.sub.i in the drawing) to the outside, and a control signal input terminal CNT for supplying a control signal to control the output timing of the output ports.
The output circuit relating to an output terminal P.sub.1 in the output ports will be described. A certain OR output (e.g., OR.sub.1) is connected to a data-input D of a D-type flip-flop circuit FF.sub.1. An output Q of the flip-flop circuit is connected to an output terminal P.sub.1 through an output buffer circuit B.sub.1. The clock input of the flip-flop circuit FF.sub.1 receives the clock signal from the clock-input terminal through an input buffer circuit. The output buffer circuit B.sub.1 is responsive to the logical level of the control signal supplied from the control signal input terminal CNT, so that the output signal of the flip- flop circuit FF.sub.1 is transmitted to the output terminal P.sub.1 or is turned to a high-impedance state. The flip-flop circuit FF.sub.1 is arranged so that the inverted output Q is fed back to a part of the input signal lines L.sub.1 -L.sub.m through a buffer circuit FB.sub.1. The output circuit relating to the other output terminals P.sub.2 -P.sub.i has the same construction as just described, and each output terminal is also referred to as a cell structure.
Complex sequential controllers and various kinds of signal processing circuits can be designed by programming certain lattice points of the AND matrix to form a shift-register or a counter from the flip-flop circuits and by feeding the output thereof back to the AND matrix.
Phase or frequency synchronization is an effective technique used in sequential controllers and signal processing circuits which are often used to control various kinds of electronic appliances. This method of phase or frequency synchronization, synchronizes the circuits to a phase or frequency of a known external signal.
According to this technique, in the case where a plurality of systems, operating in synchronism with different frequencies are made to operate in synchronism with each other, one of the systems can be made to operate in synchronism with the other system by making the one system follow the phase or frequency of a signal transferred from the other system. art. The PLL technique has been used in motor speed control systems, FM/AM transmission and reception systems, instrumentation systems for picking out a target signal from noise, and the like. A PLL device, has been developed in the form of an IC (integrated circuit).
However, conventional PLL device have always been developed as an exclusive-use device, that is, designed for a specific purpose. Accordingly, a special PLL device must be selected corresponding to the purpose. For system reconstruction, the PLL device must be replaced by another PLL device. Further, a PLL device suitable for a certain system may not be available. In short, this limits the degree of freedom in system design.